1. Field of the Invention
The present invention generally relates to a semiconductor device of excellent high frequency operation and, more particular, to a semiconductor device having high structural reliability while reducing the parasitic capacitance as low as possible.
2. Discussion of Background
As a structure of an existing semiconductor device of excellent high frequency operation, a hetero-junction bipolar transistor disclosed in JP-A No. 177966/1987 (prior art 1) has been known. In the device structure of the prior art 1, an emitter layer comprising a broad band gap N-type semiconductor layer, a base layer comprising a P-type semiconductor layer and a collector layer comprising an N-type semiconductor layer are stacked on a semi-insulating GaAs substrate successively from the side of the substrate, in which a collector electrode is disposed at the uppermost layer using an AuGe alloy, a base electrode is disposed to the base layer exposed by etching using an AuZn alloy and an emitter electrode is disposed after back side polishing of the semi-insulating GaAs substrate by back side metal vapor deposition of AuGe utilizing a via hole formed by etching that reaches the emitter layer.
While the prior art 1 does not describe device isolation, isolation of a transistor region from other regions has to be conducted, for example, by etching from the surface before the back side polishing step and the contact region to the emitter layer is smaller than the isolated transistor region.
Further, another example of forming the electrode of a transistor by way of a via hole from the back side is disclosed in JP-A No. 5620/1994 (prior art 2). In the prior art 2, the lowermost layer is a collector contact layer and device isolation is conducted by implanting hydrogen ions to the isolating region, thereby forming ion implantation layer of transforming a conductive layer into an insulating layer. In this case, the thickness of the semiconductor layer near the trench at the back side is a total of the thickness of each of the collector layer, the emitter layer, and the base layer, which is about several μm at the greatest.
However, when mesa etching is conducted for the device isolation as described above in the structure of prior art 1, production yield is lowered when the via hole and the mesa etching region are not aligned strictly at the back side etching step of forming a via hole from the back side in the inside of a transistor region to dispose a conduct region of the emitter electrode. Further, when a large alignment margin is taken in order to avoid lowering of the yield, the chip area is increased to increase the chip cost.
Prior art 2, while there is no requirement for disposing an electrode contact region to the inside of the transistor region, when the trench on the back side is made larger, the area of a thin region of several micrometers is increased to possibly deteriorate the mechanical strength.
Further, in both of the prior art 1 and the prior art 2, when adhesion with an organic adhesive such as an epoxy type paste is conducted upon chip bonding, the pressure in the via hole increases due to vapors of a solvent generated in the via hole by heating and drying of the adhesive to sometimes destroy the semiconductor region on the via hole.
Further, this results in a structure of leaving a thin semiconductor layer of about several μm or less at the largest to a portion near the electrode contact region, and stresses upon chip bonding such as by pressure increase in the via hole are concentrated in the thin semiconductor region, and induce cracks of crystals, which extend as far as the transistor region tending to cause failure due to chip destruction or transistor destruction.